Referring to FIG. 1 showing a typical flash memory, a flash memory circuit 10 comprises a memory cell array 12 consisted of a plurality of storage transistors, with each of them being a memory cell; and an X-decoder 14 and a Y-decoder 16 for selecting specified memory cells with respect to columns and rows from the memory cell array 12. The selected memory cells are connected to a data line (DL) via a select transistor 18. Voltage or current variations in the DL are detected using a sensor amplifier 20, and compared with a reference cell. Data signal OUT is then produced at an output of the sensor amplifier 20.
Considering the circuit in FIG. 1, performance distinctions arise owing to differences in actual integrated circuits when disposed at chips. Referring to FIG. 2 showing a conventional schematic view of a layout of a conventional flash memory, the layout comprises a diffusion region 32 in a memory cell array region 30, a buried diffusion layer 34 extended across the diffusion region 32, polysilicon gates 42 and 44 formed in a select transistor region 40 and at the diffusion region 32, with the polysilicon gates 42 and 44 extended in a direction parallel to the memory cell array region 30, and a plurality of select transistors 40 formed at a source/drain arranged at two sides of the polysilicon gate 44 for connecting to the buried diffusion layer 34 at the memory cell array region 30. The polysilicon gates 42 and 44 are controlled for conducting or shutting the transistors, so as to select specified memory cells. However, for that the polysilicon gates 42 and 44 are parallel to the memory cell array region 30, individual select transistors are resultantly unsymmetrical with respect to the memory cell array region 30. Through contact windows 48, the two sides of the polysilicon gates 42 and 44 are connected to the buried diffusion layer 34 and the drains/sources of the select transistors. The asymmetrical characteristic of select transistors, such as various speeds of different select transistors, is likely to cause numerous unfavorable effects and hence degrade performances. Therefore, it is a vital task as how to provide a layout of flash memory having symmetric select transistors.